In recent years, the development process of such integrated circuits (ICs) as super large scale integrated circuits (LSIs) generally utilizes computer assisted design (CAD). According to such a CAD-based development process, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip.
Before the IC chips are implemented, the placements and the layout areas of the IC chips are considered first, and then the die size of each IC chip can be determined. Furthermore, the die size will affect the manufacturing cost of the IC chip.
Therefore, it is desirable to optimize the layout area and die size of the IC chip.